1. Field of the Invention
This invention relates to a fabrication method for an integrated circuit. More particularly, the invention relates to a fabrication method for a metal-oxide-semiconductor field-effect transistor (MOSFET).
2. Description of the Related Art
In the current fabrication of an integrated circuit, a dielectric layer is formed as a device isolation structure to cover the substrate and the transistor after the completion of the manufacturing of the transistor. A consequence of having multiple layers of conductive structure separated by a dielectric material, however, is the formation of a parasitic capacitor between the transistor gate and the source/drain region. The parasitic capacitance between the conductive material separated by the insulating material in microelectronic devices contributes to effects such as the RC delay time and a decrease of the device operating speed.
The capacitance of the parasitic capacitor is related to the dielectric material used between the gate and the source/drain region. The dielectric material between the gate and the source/drain region is normally the material used for the dielectric layer and the spacer to isolate devices. The material for the dielectric layer is typically silicon dioxide (SiO.sub.2), and for the spacer it is normally silicon dioxide or silicon nitride (Si.sub.3 N.sub.4). The dielectric constant for these two types of materials are very high (silicon oxide is 3.9, and silicon nitride is 7.0). As a result, the parasitic capacitance presents between the gate electrode and the source/drain region is very high and the device operating speed is adversely affected.